Cadence gets EDA certification for TSMC 5nm and 7nm+ FinFET process technologies eeNews Europe

Cadence has worked with TSMC to certify its design offerings for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs.Cadence’s digital, signoff and custom/analog tools now have the latest Design Rule Manual (DRM) and SPICE certification for the processes. The corresponding process design kits (PDKs) can now be downloaded. Customers using Cadence’s implementation, signoff and custom/analog tools are already in production with 7nm+ projects, and there are multiple design projects underway with early 5nm customers. More information http://www.cadence.com/go/tsmc5and7nmdandsoip Related news 16nm FinFET+ Speedcore eFPGA technology validated for production Analysis: Globalfoundries to stop developing for 7nm After FinFET? imec demos Gate-all-Around Si nanowire CMOS transistors Tool base consolidates for 16 nm FinFET design at TSMC